296 lines
6.3 KiB
C++
296 lines
6.3 KiB
C++
#pragma once
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#include "esphome/core/hal.h"
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namespace esphome {
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namespace sx127x {
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enum SX127xReg : uint8_t {
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// Common registers
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REG_FIFO = 0x00,
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REG_OP_MODE = 0x01,
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REG_BITRATE_MSB = 0x02,
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REG_BITRATE_LSB = 0x03,
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REG_FDEV_MSB = 0x04,
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REG_FDEV_LSB = 0x05,
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REG_FRF_MSB = 0x06,
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REG_FRF_MID = 0x07,
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REG_FRF_LSB = 0x08,
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REG_PA_CONFIG = 0x09,
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REG_PA_RAMP = 0x0A,
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REG_DIO_MAPPING1 = 0x40,
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REG_DIO_MAPPING2 = 0x41,
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REG_VERSION = 0x42,
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// FSK/OOK registers
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REG_RX_CONFIG = 0x0D,
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REG_RSSI_THRESH = 0x10,
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REG_RX_BW = 0x12,
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REG_OOK_PEAK = 0x14,
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REG_OOK_FIX = 0x15,
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REG_OOK_AVG = 0x16,
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REG_AFC_FEI = 0x1A,
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REG_PREAMBLE_DETECT = 0x1F,
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REG_PREAMBLE_SIZE_MSB = 0x25,
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REG_PREAMBLE_SIZE_LSB = 0x26,
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REG_SYNC_CONFIG = 0x27,
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REG_SYNC_VALUE1 = 0x28,
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REG_SYNC_VALUE2 = 0x29,
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REG_SYNC_VALUE3 = 0x2A,
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REG_SYNC_VALUE4 = 0x2B,
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REG_SYNC_VALUE5 = 0x2C,
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REG_SYNC_VALUE6 = 0x2D,
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REG_SYNC_VALUE7 = 0x2E,
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REG_SYNC_VALUE8 = 0x2F,
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REG_PACKET_CONFIG_1 = 0x30,
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REG_PACKET_CONFIG_2 = 0x31,
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REG_PAYLOAD_LENGTH_LSB = 0x32,
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REG_FIFO_THRESH = 0x35,
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REG_IMAGE_CAL = 0x3B,
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// LoRa registers
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REG_FIFO_ADDR_PTR = 0x0D,
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REG_FIFO_TX_BASE_ADDR = 0x0E,
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REG_FIFO_RX_BASE_ADDR = 0x0F,
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REG_FIFO_RX_CURR_ADDR = 0x10,
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REG_IRQ_FLAGS_MASK = 0x11,
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REG_IRQ_FLAGS = 0x12,
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REG_NB_RX_BYTES = 0x13,
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REG_MODEM_STAT = 0x18,
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REG_PKT_SNR_VALUE = 0x19,
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REG_PKT_RSSI_VALUE = 0x1A,
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REG_RSSI_VALUE = 0x1B,
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REG_HOP_CHANNEL = 0x1C,
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REG_MODEM_CONFIG1 = 0x1D,
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REG_MODEM_CONFIG2 = 0x1E,
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REG_SYMB_TIMEOUT_LSB = 0x1F,
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REG_PREAMBLE_LEN_MSB = 0x20,
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REG_PREAMBLE_LEN_LSB = 0x21,
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REG_PAYLOAD_LENGTH = 0x22,
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REG_HOP_PERIOD = 0x24,
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REG_FIFO_RX_BYTE_ADDR = 0x25,
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REG_MODEM_CONFIG3 = 0x26,
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REG_FEI_MSB = 0x28,
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REG_FEI_MIB = 0x29,
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REG_FEI_LSB = 0x2A,
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REG_DETECT_OPTIMIZE = 0x31,
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REG_INVERT_IQ = 0x33,
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REG_DETECT_THRESHOLD = 0x37,
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REG_SYNC_WORD = 0x39,
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};
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enum SX127xOpMode : uint8_t {
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MOD_LORA = 0x80,
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ACCESS_FSK_REGS = 0x40,
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ACCESS_LORA_REGS = 0x00,
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MOD_OOK = 0x20,
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MOD_FSK = 0x00,
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ACCESS_LF_REGS = 0x08,
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ACCESS_HF_REGS = 0x00,
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MODE_CAD = 0x07,
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MODE_RX_SINGLE = 0x06,
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MODE_RX = 0x05,
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MODE_RX_FS = 0x04,
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MODE_TX = 0x03,
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MODE_TX_FS = 0x02,
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MODE_STDBY = 0x01,
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MODE_SLEEP = 0x00,
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MODE_MASK = 0x07,
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};
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enum SX127xPaConfig : uint8_t {
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PA_PIN_BOOST = 0x80,
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PA_PIN_RFO = 0x00,
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PA_MAX_POWER = 0x70,
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};
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enum SX127xPaRamp : uint8_t {
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CUTOFF_BR_X_2 = 0x40,
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CUTOFF_BR_X_1 = 0x20,
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GAUSSIAN_BT_0_3 = 0x60,
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GAUSSIAN_BT_0_5 = 0x40,
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GAUSSIAN_BT_1_0 = 0x20,
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SHAPING_NONE = 0x00,
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PA_RAMP_10 = 0x0F,
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PA_RAMP_12 = 0x0E,
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PA_RAMP_15 = 0x0D,
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PA_RAMP_20 = 0x0C,
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PA_RAMP_25 = 0x0B,
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PA_RAMP_31 = 0x0A,
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PA_RAMP_40 = 0x09,
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PA_RAMP_50 = 0x08,
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PA_RAMP_62 = 0x07,
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PA_RAMP_100 = 0x06,
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PA_RAMP_125 = 0x05,
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PA_RAMP_250 = 0x04,
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PA_RAMP_500 = 0x03,
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PA_RAMP_1000 = 0x02,
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PA_RAMP_2000 = 0x01,
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PA_RAMP_3400 = 0x00,
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};
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enum SX127xDioMapping1 : uint8_t {
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DIO0_MAPPING_00 = 0x00,
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DIO0_MAPPING_01 = 0x40,
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DIO0_MAPPING_10 = 0x80,
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DIO0_MAPPING_11 = 0xC0,
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};
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enum SX127xRxConfig : uint8_t {
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RESTART_ON_COLLISION = 0x80,
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RESTART_NO_LOCK = 0x40,
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RESTART_PLL_LOCK = 0x20,
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AFC_AUTO_ON = 0x10,
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AGC_AUTO_ON = 0x08,
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TRIGGER_NONE = 0x00,
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TRIGGER_RSSI = 0x01,
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TRIGGER_PREAMBLE = 0x06,
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TRIGGER_ALL = 0x07,
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};
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enum SX127xRxBw : uint8_t {
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RX_BW_2_6 = 0x17,
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RX_BW_3_1 = 0x0F,
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RX_BW_3_9 = 0x07,
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RX_BW_5_2 = 0x16,
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RX_BW_6_3 = 0x0E,
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RX_BW_7_8 = 0x06,
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RX_BW_10_4 = 0x15,
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RX_BW_12_5 = 0x0D,
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RX_BW_15_6 = 0x05,
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RX_BW_20_8 = 0x14,
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RX_BW_25_0 = 0x0C,
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RX_BW_31_3 = 0x04,
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RX_BW_41_7 = 0x13,
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RX_BW_50_0 = 0x0B,
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RX_BW_62_5 = 0x03,
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RX_BW_83_3 = 0x12,
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RX_BW_100_0 = 0x0A,
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RX_BW_125_0 = 0x02,
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RX_BW_166_7 = 0x11,
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RX_BW_200_0 = 0x09,
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RX_BW_250_0 = 0x01,
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};
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enum SX127xOokPeak : uint8_t {
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BIT_SYNC_ON = 0x20,
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BIT_SYNC_OFF = 0x00,
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OOK_THRESH_AVG = 0x10,
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OOK_THRESH_PEAK = 0x08,
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OOK_THRESH_FIXED = 0x00,
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OOK_THRESH_STEP_6_0 = 0x07,
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OOK_THRESH_STEP_5_0 = 0x06,
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OOK_THRESH_STEP_4_0 = 0x05,
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OOK_THRESH_STEP_3_0 = 0x04,
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OOK_THRESH_STEP_2_0 = 0x03,
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OOK_THRESH_STEP_1_5 = 0x02,
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OOK_THRESH_STEP_1_0 = 0x01,
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OOK_THRESH_STEP_0_5 = 0x00,
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};
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enum SX127xOokAvg : uint8_t {
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OOK_THRESH_DEC_16 = 0xE0,
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OOK_THRESH_DEC_8 = 0xC0,
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OOK_THRESH_DEC_4 = 0xA0,
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OOK_THRESH_DEC_2 = 0x80,
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OOK_THRESH_DEC_1_8 = 0x60,
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OOK_THRESH_DEC_1_4 = 0x40,
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OOK_THRESH_DEC_1_2 = 0x20,
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OOK_THRESH_DEC_1 = 0x00,
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OOK_AVG_RESERVED = 0x10,
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};
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enum SX127xAfcFei : uint8_t {
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AFC_AUTO_CLEAR_ON = 0x01,
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};
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enum SX127xPreambleDetect : uint8_t {
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PREAMBLE_DETECTOR_ON = 0x80,
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PREAMBLE_DETECTOR_OFF = 0x00,
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PREAMBLE_DETECTOR_SIZE_SHIFT = 5,
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PREAMBLE_DETECTOR_TOL_SHIFT = 0,
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};
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enum SX127xSyncConfig : uint8_t {
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AUTO_RESTART_PLL_LOCK = 0x80,
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AUTO_RESTART_NO_LOCK = 0x40,
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AUTO_RESTART_OFF = 0x00,
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PREAMBLE_55 = 0x20,
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PREAMBLE_AA = 0x00,
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SYNC_ON = 0x10,
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SYNC_OFF = 0x00,
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};
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enum SX127xPacketConfig1 : uint8_t {
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VARIABLE_LENGTH = 0x80,
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FIXED_LENGTH = 0x00,
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CRC_ON = 0x10,
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CRC_OFF = 0x00,
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};
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enum SX127xPacketConfig2 : uint8_t {
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CONTINUOUS_MODE = 0x00,
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PACKET_MODE = 0x40,
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};
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enum SX127xFifoThresh : uint8_t {
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TX_START_FIFO_EMPTY = 0x80,
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TX_START_FIFO_LEVEL = 0x00,
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};
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enum SX127xImageCal : uint8_t {
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AUTO_IMAGE_CAL_ON = 0x80,
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IMAGE_CAL_START = 0x40,
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IMAGE_CAL_RUNNING = 0x20,
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TEMP_CHANGE = 0x08,
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TEMP_THRESHOLD_20C = 0x06,
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TEMP_THRESHOLD_15C = 0x04,
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TEMP_THRESHOLD_10C = 0x02,
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TEMP_THRESHOLD_5C = 0x00,
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TEMP_MONITOR_OFF = 0x01,
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TEMP_MONITOR_ON = 0x00,
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};
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enum SX127xIrqFlags : uint8_t {
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RX_TIMEOUT = 0x80,
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RX_DONE = 0x40,
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PAYLOAD_CRC_ERROR = 0x20,
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VALID_HEADER = 0x10,
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TX_DONE = 0x08,
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CAD_DONE = 0x04,
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FHSS_CHANGE_CHANNEL = 0x02,
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CAD_DETECTED = 0x01,
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};
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enum SX127xModemCfg1 : uint8_t {
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BW_7_8 = 0x00,
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BW_10_4 = 0x10,
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BW_15_6 = 0x20,
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BW_20_8 = 0x30,
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BW_31_3 = 0x40,
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BW_41_7 = 0x50,
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BW_62_5 = 0x60,
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BW_125_0 = 0x70,
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BW_250_0 = 0x80,
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BW_500_0 = 0x90,
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CODING_RATE_4_5 = 0x02,
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CODING_RATE_4_6 = 0x04,
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CODING_RATE_4_7 = 0x06,
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CODING_RATE_4_8 = 0x08,
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IMPLICIT_HEADER = 0x01,
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EXPLICIT_HEADER = 0x00,
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};
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enum SX127xModemCfg2 : uint8_t {
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SPREADING_FACTOR_SHIFT = 4,
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TX_CONTINOUS_MODE = 0x08,
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RX_PAYLOAD_CRC_ON = 0x04,
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RX_PAYLOAD_CRC_OFF = 0x00,
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};
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enum SX127xModemCfg3 : uint8_t {
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LOW_DATA_RATE_OPTIMIZE_ON = 0x08,
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MODEM_AGC_AUTO_ON = 0x04,
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};
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} // namespace sx127x
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} // namespace esphome
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