671 lines
14 KiB
C++
671 lines
14 KiB
C++
#pragma once
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#include <cinttypes>
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namespace esphome::cc1101 {
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static constexpr float XTAL_FREQUENCY = 26000000;
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static constexpr float RSSI_OFFSET = 74.0f;
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static constexpr float RSSI_STEP = 0.5f;
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static constexpr uint8_t FSCAL1_PLL_NOT_LOCKED = 0x3F;
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static constexpr uint8_t PLL_LOCK_RETRIES = 3;
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static constexpr uint8_t STATUS_CRC_OK_MASK = 0x80;
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static constexpr uint8_t STATUS_LQI_MASK = 0x7F;
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static constexpr uint8_t BUS_BURST = 0x40;
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static constexpr uint8_t BUS_READ = 0x80;
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static constexpr uint8_t BUS_WRITE = 0x00;
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static constexpr uint8_t BYTES_IN_RXFIFO = 0x7F; // byte number in RXfifo
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static constexpr size_t PA_TABLE_SIZE = 8;
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enum class Register : uint8_t {
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IOCFG2 = 0x00, // GDO2 output pin configuration
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IOCFG1 = 0x01, // GDO1 output pin configuration
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IOCFG0 = 0x02, // GDO0 output pin configuration
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FIFOTHR = 0x03, // RX FIFO and TX FIFO thresholds
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SYNC1 = 0x04, // Sync word, high INT8U
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SYNC0 = 0x05, // Sync word, low INT8U
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PKTLEN = 0x06, // Packet length
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PKTCTRL1 = 0x07, // Packet automation control
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PKTCTRL0 = 0x08, // Packet automation control
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ADDR = 0x09, // Device address
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CHANNR = 0x0A, // Channel number
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FSCTRL1 = 0x0B, // Frequency synthesizer control
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FSCTRL0 = 0x0C, // Frequency synthesizer control
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FREQ2 = 0x0D, // Frequency control word, high INT8U
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FREQ1 = 0x0E, // Frequency control word, middle INT8U
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FREQ0 = 0x0F, // Frequency control word, low INT8U
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MDMCFG4 = 0x10, // Modem configuration
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MDMCFG3 = 0x11, // Modem configuration
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MDMCFG2 = 0x12, // Modem configuration
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MDMCFG1 = 0x13, // Modem configuration
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MDMCFG0 = 0x14, // Modem configuration
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DEVIATN = 0x15, // Modem deviation setting
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MCSM2 = 0x16, // Main Radio Control State Machine configuration
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MCSM1 = 0x17, // Main Radio Control State Machine configuration
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MCSM0 = 0x18, // Main Radio Control State Machine configuration
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FOCCFG = 0x19, // Frequency Offset Compensation configuration
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BSCFG = 0x1A, // Bit Synchronization configuration
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AGCCTRL2 = 0x1B, // AGC control
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AGCCTRL1 = 0x1C, // AGC control
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AGCCTRL0 = 0x1D, // AGC control
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WOREVT1 = 0x1E, // High INT8U Event 0 timeout
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WOREVT0 = 0x1F, // Low INT8U Event 0 timeout
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WORCTRL = 0x20, // Wake On Radio control
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FREND1 = 0x21, // Front end RX configuration
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FREND0 = 0x22, // Front end TX configuration
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FSCAL3 = 0x23, // Frequency synthesizer calibration
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FSCAL2 = 0x24, // Frequency synthesizer calibration
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FSCAL1 = 0x25, // Frequency synthesizer calibration
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FSCAL0 = 0x26, // Frequency synthesizer calibration
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RCCTRL1 = 0x27, // RC oscillator configuration
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RCCTRL0 = 0x28, // RC oscillator configuration
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FSTEST = 0x29, // Frequency synthesizer calibration control
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PTEST = 0x2A, // Production test
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AGCTEST = 0x2B, // AGC test
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TEST2 = 0x2C, // Various test settings
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TEST1 = 0x2D, // Various test settings
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TEST0 = 0x2E, // Various test settings
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UNUSED = 0x2F,
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PARTNUM = 0x30,
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VERSION = 0x31,
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FREQEST = 0x32,
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LQI = 0x33,
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RSSI = 0x34,
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MARCSTATE = 0x35,
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WORTIME1 = 0x36,
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WORTIME0 = 0x37,
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PKTSTATUS = 0x38,
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VCO_VC_DAC = 0x39,
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TXBYTES = 0x3A,
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RXBYTES = 0x3B,
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RCCTRL1_STATUS = 0x3C,
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RCCTRL0_STATUS = 0x3D,
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PATABLE = 0x3E,
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FIFO = 0x3F,
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};
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enum class Command : uint8_t {
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RES = 0x30, // Reset chip.
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FSTXON = 0x31, // Enable and calibrate frequency synthesizer
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XOFF = 0x32, // Turn off crystal oscillator.
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CAL = 0x33, // Calibrate frequency synthesizer and turn it off
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RX = 0x34, // Enable RX.
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TX = 0x35, // Enable TX.
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IDLE = 0x36, // Exit RX / TX
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// 0x37 is RESERVED / UNDEFINED in CC1101 Datasheet
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WOR = 0x38, // Start automatic RX polling sequence (Wake-on-Radio)
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PWD = 0x39, // Enter power down mode when CSn goes high.
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FRX = 0x3A, // Flush the RX FIFO buffer.
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FTX = 0x3B, // Flush the TX FIFO buffer.
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WORRST = 0x3C, // Reset real time clock.
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NOP = 0x3D, // No operation.
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};
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enum class State : uint8_t {
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SLEEP,
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IDLE,
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XOFF,
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VCOON_MC,
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REGON_MC,
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MANCAL,
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VCOON,
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REGON,
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STARTCAL,
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BWBOOST,
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FS_LOCK,
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IFADCON,
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ENDCAL,
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RX,
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RX_END,
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RX_RST,
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TXRX_SWITCH,
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RXFIFO_OVERFLOW,
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FSTXON,
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TX,
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TX_END,
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RXTX_SWITCH,
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TXFIFO_UNDERFLOW,
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};
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enum class RxAttenuation : uint8_t {
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RX_ATTENUATION_0DB,
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RX_ATTENUATION_6DB,
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RX_ATTENUATION_12DB,
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RX_ATTENUATION_18DB,
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};
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enum class SyncMode : uint8_t {
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SYNC_MODE_NONE,
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SYNC_MODE_15_16,
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SYNC_MODE_16_16,
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SYNC_MODE_30_32,
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SYNC_MODE_NONE_CS,
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SYNC_MODE_15_16_CS,
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SYNC_MODE_16_16_CS,
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SYNC_MODE_30_32_CS,
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};
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enum class Modulation : uint8_t {
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MODULATION_2_FSK,
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MODULATION_GFSK,
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MODULATION_UNUSED_2,
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MODULATION_ASK_OOK,
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MODULATION_4_FSK,
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MODULATION_UNUSED_5,
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MODULATION_UNUSED_6,
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MODULATION_MSK,
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};
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enum class MagnTarget : uint8_t {
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MAGN_TARGET_24DB,
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MAGN_TARGET_27DB,
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MAGN_TARGET_30DB,
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MAGN_TARGET_33DB,
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MAGN_TARGET_36DB,
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MAGN_TARGET_38DB,
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MAGN_TARGET_40DB,
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MAGN_TARGET_42DB,
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};
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enum class MaxLnaGain : uint8_t {
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MAX_LNA_GAIN_DEFAULT,
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MAX_LNA_GAIN_MINUS_2P6DB,
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MAX_LNA_GAIN_MINUS_6P1DB,
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MAX_LNA_GAIN_MINUS_7P4DB,
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MAX_LNA_GAIN_MINUS_9P2DB,
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MAX_LNA_GAIN_MINUS_11P5DB,
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MAX_LNA_GAIN_MINUS_14P6DB,
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MAX_LNA_GAIN_MINUS_17P1DB,
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};
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enum class MaxDvgaGain : uint8_t {
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MAX_DVGA_GAIN_DEFAULT,
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MAX_DVGA_GAIN_MINUS_1,
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MAX_DVGA_GAIN_MINUS_2,
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MAX_DVGA_GAIN_MINUS_3,
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};
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enum class CarrierSenseRelThr : uint8_t {
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CARRIER_SENSE_REL_THR_DEFAULT,
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CARRIER_SENSE_REL_THR_PLUS_6DB,
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CARRIER_SENSE_REL_THR_PLUS_10DB,
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CARRIER_SENSE_REL_THR_PLUS_14DB,
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};
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enum class FilterLengthFskMsk : uint8_t {
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FILTER_LENGTH_8DB,
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FILTER_LENGTH_16DB,
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FILTER_LENGTH_32DB,
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FILTER_LENGTH_64DB,
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};
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enum class FilterLengthAskOok : uint8_t {
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FILTER_LENGTH_4DB,
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FILTER_LENGTH_8DB,
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FILTER_LENGTH_12DB,
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FILTER_LENGTH_16DB,
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};
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enum class Freeze : uint8_t {
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FREEZE_DEFAULT,
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FREEZE_ON_SYNC,
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FREEZE_ANALOG_ONLY,
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FREEZE_ANALOG_AND_DIGITAL,
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};
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enum class WaitTime : uint8_t {
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WAIT_TIME_8_SAMPLES,
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WAIT_TIME_16_SAMPLES,
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WAIT_TIME_24_SAMPLES,
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WAIT_TIME_32_SAMPLES,
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};
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enum class HystLevel : uint8_t {
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HYST_LEVEL_NONE,
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HYST_LEVEL_LOW,
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HYST_LEVEL_MEDIUM,
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HYST_LEVEL_HIGH,
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};
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enum class PacketFormat : uint8_t {
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PACKET_FORMAT_FIFO,
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PACKET_FORMAT_SYNC_SERIAL,
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PACKET_FORMAT_RANDOM_TX,
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PACKET_FORMAT_ASYNC_SERIAL,
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};
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enum class LengthConfig : uint8_t {
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LENGTH_CONFIG_FIXED,
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LENGTH_CONFIG_VARIABLE,
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LENGTH_CONFIG_INFINITE,
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};
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struct __attribute__((packed)) CC1101State {
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// Byte array accessors for bulk SPI transfers
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uint8_t *regs() { return reinterpret_cast<uint8_t *>(this); }
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const uint8_t *regs() const { return reinterpret_cast<const uint8_t *>(this); }
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// 0x00
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union {
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uint8_t IOCFG2;
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struct {
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uint8_t GDO2_CFG : 6;
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uint8_t GDO2_INV : 1;
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uint8_t : 1;
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};
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};
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// 0x01
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union {
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uint8_t IOCFG1;
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struct {
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uint8_t GDO1_CFG : 6;
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uint8_t GDO1_INV : 1;
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uint8_t GDO_DS : 1; // GDO, not GD0
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};
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};
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// 0x02
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union {
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uint8_t IOCFG0;
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struct {
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uint8_t GDO0_CFG : 6;
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uint8_t GDO0_INV : 1;
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uint8_t TEMP_SENSOR_ENABLE : 1;
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};
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};
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// 0x03
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union {
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uint8_t FIFOTHR;
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struct {
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uint8_t FIFO_THR : 4;
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uint8_t CLOSE_IN_RX : 2; // RxAttenuation
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uint8_t ADC_RETENTION : 1;
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uint8_t : 1;
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};
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};
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// 0x04
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uint8_t SYNC1;
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// 0x05
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uint8_t SYNC0;
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// 0x06
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uint8_t PKTLEN;
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// 0x07
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union {
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uint8_t PKTCTRL1;
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struct {
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uint8_t ADR_CHK : 2;
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uint8_t APPEND_STATUS : 1;
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uint8_t CRC_AUTOFLUSH : 1;
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uint8_t : 1;
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uint8_t PQT : 3;
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};
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};
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// 0x08
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union {
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uint8_t PKTCTRL0;
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struct {
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uint8_t LENGTH_CONFIG : 2;
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uint8_t CRC_EN : 1;
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uint8_t : 1;
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uint8_t PKT_FORMAT : 2;
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uint8_t WHITE_DATA : 1;
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uint8_t : 1;
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};
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};
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// 0x09
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uint8_t ADDR;
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// 0x0A
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uint8_t CHANNR;
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// 0x0B
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union {
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uint8_t FSCTRL1;
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struct {
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uint8_t FREQ_IF : 5;
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uint8_t RESERVED : 1; // hm?
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uint8_t : 2;
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};
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};
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// 0x0C
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uint8_t FSCTRL0;
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// 0x0D
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uint8_t FREQ2; // [7:6] always zero
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// 0x0E
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uint8_t FREQ1;
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// 0x0F
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uint8_t FREQ0;
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// 0x10
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union {
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uint8_t MDMCFG4;
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struct {
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uint8_t DRATE_E : 4;
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uint8_t CHANBW_M : 2;
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uint8_t CHANBW_E : 2;
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};
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};
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// 0x11
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union {
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uint8_t MDMCFG3;
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struct {
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uint8_t DRATE_M : 8;
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};
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};
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// 0x12
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union {
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uint8_t MDMCFG2;
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struct {
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uint8_t SYNC_MODE : 2;
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uint8_t CARRIER_SENSE_ABOVE_THRESHOLD : 1;
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uint8_t MANCHESTER_EN : 1;
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uint8_t MOD_FORMAT : 3; // Modulation
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uint8_t DEM_DCFILT_OFF : 1;
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};
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};
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// 0x13
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union {
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uint8_t MDMCFG1;
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struct {
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uint8_t CHANSPC_E : 2;
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uint8_t : 2;
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uint8_t NUM_PREAMBLE : 3;
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uint8_t FEC_EN : 1;
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};
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};
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// 0x14
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union {
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uint8_t MDMCFG0;
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struct {
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uint8_t CHANSPC_M : 8;
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};
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};
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// 0x15
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union {
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uint8_t DEVIATN;
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struct {
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uint8_t DEVIATION_M : 3;
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uint8_t : 1;
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uint8_t DEVIATION_E : 3;
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uint8_t : 1;
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};
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};
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// 0x16
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union {
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uint8_t MCSM2;
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struct {
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uint8_t RX_TIME : 3;
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uint8_t RX_TIME_QUAL : 1;
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uint8_t RX_TIME_RSSI : 1;
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uint8_t : 3;
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};
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};
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// 0x17
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union {
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uint8_t MCSM1;
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struct {
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uint8_t TXOFF_MODE : 2;
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uint8_t RXOFF_MODE : 2;
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uint8_t CCA_MODE : 2;
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uint8_t : 2;
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};
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};
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// 0x18
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union {
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uint8_t MCSM0;
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struct {
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uint8_t XOSC_FORCE_ON : 1;
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uint8_t PIN_CTRL_EN : 1;
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uint8_t PO_TIMEOUT : 2;
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uint8_t FS_AUTOCAL : 2;
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uint8_t : 2;
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};
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};
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// 0x19
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union {
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uint8_t FOCCFG;
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struct {
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uint8_t FOC_LIMIT : 2;
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uint8_t FOC_POST_K : 1;
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uint8_t FOC_PRE_K : 2;
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uint8_t FOC_BS_CS_GATE : 1;
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uint8_t : 2;
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};
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};
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// 0x1A
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union {
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uint8_t BSCFG;
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struct {
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uint8_t BS_LIMIT : 2;
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uint8_t BS_POST_KP : 1;
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uint8_t BS_POST_KI : 1;
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uint8_t BS_PRE_KP : 2;
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uint8_t BS_PRE_KI : 2;
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};
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};
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// 0x1B
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union {
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uint8_t AGCCTRL2;
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struct {
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uint8_t MAGN_TARGET : 3; // MagnTarget
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uint8_t MAX_LNA_GAIN : 3; // MaxLnaGain
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uint8_t MAX_DVGA_GAIN : 2; // MaxDvgaGain
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};
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};
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// 0x1C
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union {
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uint8_t AGCCTRL1;
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struct {
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uint8_t CARRIER_SENSE_ABS_THR : 4;
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uint8_t CARRIER_SENSE_REL_THR : 2; // CarrierSenseRelThr
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uint8_t AGC_LNA_PRIORITY : 1;
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uint8_t : 1;
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};
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};
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// 0x1D
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union {
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uint8_t AGCCTRL0;
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struct {
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uint8_t FILTER_LENGTH : 2; // FilterLengthFskMsk or FilterLengthAskOok
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uint8_t AGC_FREEZE : 2; // Freeze
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uint8_t WAIT_TIME : 2; // WaitTime
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uint8_t HYST_LEVEL : 2; // HystLevel
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};
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};
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// 0x1E
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uint8_t WOREVT1;
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// 0x1F
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uint8_t WOREVT0;
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// 0x20
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union {
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uint8_t WORCTRL;
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struct {
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uint8_t WOR_RES : 2;
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uint8_t : 1;
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uint8_t RC_CAL : 1;
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uint8_t EVENT1 : 3;
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uint8_t RC_PD : 1;
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};
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};
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// 0x21
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union {
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uint8_t FREND1;
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struct {
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uint8_t MIX_CURRENT : 2;
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uint8_t LODIV_BUF_CURRENT_RX : 2;
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uint8_t LNA2MIX_CURRENT : 2;
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uint8_t LNA_CURRENT : 2;
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};
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};
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// 0x22
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union {
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uint8_t FREND0;
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struct {
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uint8_t PA_POWER : 3;
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uint8_t : 1;
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uint8_t LODIV_BUF_CURRENT_TX : 2;
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uint8_t : 2;
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};
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};
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// 0x23
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union {
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uint8_t FSCAL3;
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struct {
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uint8_t FSCAL3_LO : 4;
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uint8_t CHP_CURR_CAL_EN : 2; // Disable charge pump calibration stage when 0.
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uint8_t FSCAL3_HI : 2;
|
|
};
|
|
};
|
|
// 0x24
|
|
union {
|
|
// uint8_t FSCAL2;
|
|
struct {
|
|
uint8_t FSCAL2 : 5;
|
|
uint8_t VCO_CORE_H_EN : 1;
|
|
uint8_t : 2;
|
|
};
|
|
};
|
|
// 0x25
|
|
union {
|
|
// uint8_t FSCAL1;
|
|
struct {
|
|
uint8_t FSCAL1 : 6;
|
|
uint8_t : 2;
|
|
};
|
|
};
|
|
// 0x26
|
|
union {
|
|
// uint8_t FSCAL0;
|
|
struct {
|
|
uint8_t FSCAL0 : 7;
|
|
uint8_t : 1;
|
|
};
|
|
};
|
|
// 0x27
|
|
union {
|
|
// uint8_t RCCTRL1;
|
|
struct {
|
|
uint8_t RCCTRL1 : 7;
|
|
uint8_t : 1;
|
|
};
|
|
};
|
|
// 0x28
|
|
union {
|
|
// uint8_t RCCTRL0;
|
|
struct {
|
|
uint8_t RCCTRL0 : 7;
|
|
uint8_t : 1;
|
|
};
|
|
};
|
|
// 0x29
|
|
uint8_t FSTEST;
|
|
// 0x2A
|
|
uint8_t PTEST;
|
|
// 0x2B
|
|
uint8_t AGCTEST;
|
|
// 0x2C
|
|
uint8_t TEST2;
|
|
// 0x2D
|
|
uint8_t TEST1;
|
|
// 0x2E
|
|
union {
|
|
uint8_t TEST0;
|
|
struct {
|
|
uint8_t TEST0_LO : 1;
|
|
uint8_t VCO_SEL_CAL_EN : 1; // Enable VCO selection calibration stage when 1
|
|
uint8_t TEST0_HI : 6;
|
|
};
|
|
};
|
|
// 0x2F
|
|
uint8_t REG_2F;
|
|
// 0x30
|
|
uint8_t PARTNUM;
|
|
// 0x31
|
|
uint8_t VERSION;
|
|
// 0x32
|
|
union {
|
|
uint8_t FREQEST;
|
|
struct {
|
|
int8_t FREQOFF_EST : 8;
|
|
};
|
|
};
|
|
// 0x33
|
|
union {
|
|
uint8_t LQI;
|
|
struct {
|
|
uint8_t LQI_EST : 7;
|
|
uint8_t LQI_CRC_OK : 1;
|
|
};
|
|
};
|
|
// 0x34
|
|
int8_t RSSI;
|
|
// 0x35
|
|
union {
|
|
// uint8_t MARCSTATE;
|
|
struct {
|
|
uint8_t MARC_STATE : 5; // State
|
|
uint8_t : 3;
|
|
};
|
|
};
|
|
// 0x36
|
|
uint8_t WORTIME1;
|
|
// 0x37
|
|
uint8_t WORTIME0;
|
|
// 0x38
|
|
union {
|
|
uint8_t PKTSTATUS;
|
|
struct {
|
|
uint8_t GDO0 : 1;
|
|
uint8_t : 1;
|
|
uint8_t GDO2 : 1;
|
|
uint8_t SFD : 1;
|
|
uint8_t CCA : 1;
|
|
uint8_t PQT_REACHED : 1;
|
|
uint8_t CS : 1;
|
|
uint8_t CRC_OK : 1; // same as LQI_CRC_OK?
|
|
};
|
|
};
|
|
// 0x39
|
|
uint8_t VCO_VC_DAC;
|
|
// 0x3A
|
|
union {
|
|
uint8_t TXBYTES;
|
|
struct {
|
|
uint8_t NUM_TXBYTES : 7;
|
|
uint8_t TXFIFO_UNDERFLOW : 1;
|
|
};
|
|
};
|
|
// 0x3B
|
|
union {
|
|
uint8_t RXBYTES;
|
|
struct {
|
|
uint8_t NUM_RXBYTES : 7;
|
|
uint8_t RXFIFO_OVERFLOW : 1;
|
|
};
|
|
};
|
|
// 0x3C
|
|
union {
|
|
// uint8_t RCCTRL1_STATUS;
|
|
struct {
|
|
uint8_t RCCTRL1_STATUS : 7;
|
|
uint8_t : 1;
|
|
};
|
|
};
|
|
// 0x3D
|
|
union {
|
|
// uint8_t RCCTRL0_STATUS;
|
|
struct {
|
|
uint8_t RCCTRL0_STATUS : 7;
|
|
uint8_t : 1;
|
|
};
|
|
};
|
|
// 0x3E
|
|
uint8_t REG_3E;
|
|
// 0x3F
|
|
uint8_t REG_3F;
|
|
};
|
|
|
|
static_assert(sizeof(CC1101State) == 0x40, "CC1101State size mismatch");
|
|
|
|
} // namespace esphome::cc1101
|